Semiconductor package and semiconductor device

ABSTRACT

The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed. Thereby, the molding compound covers the entire surface of the substrate, so that the bonding pads on the surface of the substrate will not be polluted.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.11/828,351, filed on Jul. 26, 2007, which claims the benefit of TaiwanPatent Application No. 095135866, filed on Sep. 27, 2006, thedisclosures of which are incorporated herein by reference in theirentirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor package and a method ofmaking the same, and particularly to a semiconductor package comprisinga molding compound with different heights and a semiconductor devicecomprising the semiconductor package and methods of making the same.

2. Description of the Prior Art

Please refer to FIG. 1 showing a schematic diagram of a conventionalsemiconductor device consisting of stacked packages. The conventionalsemiconductor device 1 comprises a first package 10 and a second package20. The first package 10 comprises a first substrate 11, a first chip12, a plurality of first conductive wires 13, a first molding compound14, and a plurality of first solder balls 15. The first substrate 11 hasan upper surface 111, a lower surface 112, and a plurality of first pads113. The first pads 113 are disposed on the upper surface 111 of thefirst substrate 11. The first chip 12 is adhered to the upper surface111 of the first substrate 11 and electrically connected to the uppersurface 111 of the first substrate 11 by the first conductive wires 13.The first molding compound 14 encapsulates the first chip 12, the firstconductive wires 13, and a part of the upper surface 111 of the firstsubstrate 11, and the first pads 113 are exposed. The first solder balls15 are on the lower surface 112 of the first substrate 11.

The second package 20 is stacked on the first package 10. The secondpackage 20 comprises a second substrate 21, a second chip 22, aplurality of second conductive wires 23, a second molding compound 24,and a plurality of second solder balls 25. The second substrate 21 hasan upper surface 211, a lower surface 212, and a plurality of secondpads 213. The second pads 213 are disposed on the lower surface 212 ofthe second substrate 21. The second chip 22 is adhered to the uppersurface 211 of the second substrate 21 and electrically connected to theupper surface 211 of the second substrate 21 by the second conductivewires 23. The second molding compound 24 encapsulates the second chip22, the second conductive wires 23, and the upper surface 211 of thesecond substrate 21. The upper ends of the second solder balls 25 areconnected to the second pads 213 on the lower surface 212 of the secondsubstrate 21, and the lower ends are connected to the first pads 113 onthe upper surface 111 of the first substrate 11.

One of the drawbacks of the conventional semiconductor device 1 is thatthe area encapsulated by the first molding compound 14 in the firstpackage 10 is smaller than that encapsulated by the second moldingcompound 24 in the second package 20. As a result, two different moldsare required in the molding processes for the first package 10 and thesecond package 20. The cost is high for making a mold. Molds ofdifferent sizes are often needed for molding processes to make differentpackage devices. Accordingly, the production cost will be dramaticallyincreased. Moreover, in the first package 10, there is an included angleof about 60 degrees between the sidewall of the first molding compound14 and the first substrate 11. The included angle is namely the draftangle of the mold. Furthermore, the top surface of the first moldingcompound 14 has a mold insert gate mark. In addition, in the moldingprocess for the first package 10, the first molding compound 14 tends tooverflow onto the upper surface 111 of the first substrate 11 to pollutethe first pads 113.

Therefore, it is necessary to provide a novel and progressivesemiconductor package and semiconductor device and method of making thesame to solve the aforesaid problems.

SUMMARY OF THE INVENTION

One main objective of the present invention is to provide a method ofmaking a semiconductor package comprising the following steps of:providing a first substrate having a first surface and a second surface;attaching a first chip to the first surface of the first substrate;forming a plurality of first connecting elements for electricallyconnecting the first chip and the first substrate; forming a pluralityof first conductive bodies on the first surface of the first substrate;forming a first molding compound for encapsulating the first surface ofthe first substrate, the first chip, the first connecting elements, andthe first conductive bodies; and removing a part of a border portion ofthe first molding compound, so that the first molding compound has atleast two heights and one end of each of the first conductive bodies isexposed.

Another objective of the present invention is to provide a semiconductorpackage, which comprises a substrate, a chip, a plurality of connectingelements, a plurality of first conductive bodies, and a moldingcompound. The substrate has a first surface and a second surface. Thechip is attached to the first surface of the substrate. The connectingelements electrically connect the chip and the substrate. The firstconductive bodies are disposed on the first surface of the substrate.The molding compound encapsulates the first surface of the substrate,the chip, the connecting elements, and the first conductive bodies. Themolding compound has at least two heights and one end of each of thefirst conductive bodies is exposed. Thereby, the molding compoundencapsulates the entire first surface of the substrate, and the pads onthe first surface will not be polluted.

Still another objective of the present invention is to provide asemiconductor device, which comprises a first package and a secondpackage. The first package is the semiconductor package as describedabove. The second package is stacked on the first package. In anembodiment, the size of the second package is the same as that of thefirst package. Thus, only one mold is required to perform both themolding processes for the second package and the first package.Accordingly, the production cost will be reduced.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic diagram of a conventional semiconductor deviceconsisting of stacked packages;

FIG. 2 shows a flow chart of the method of making a semiconductor deviceaccording to the present invention; and

FIGS. 3 to 8 show schematic step by step diagrams illustrating themethod of making a semiconductor device according to the presentinvention.

DETAILED DESCRIPTION

Please refer to FIG. 2 showing a flow chart of the method of making asemiconductor device according to the present invention. Also refer toFIG. 3. In Step S201, a first substrate 31 is provided. The firstsubstrate 31 has a first surface 311, a second surface 312, a pluralityof first pads 313, and a plurality of second pads 314. The first pads313 are on the first surface 311, and the second pads 314 are on thesecond surface 312. In Step S202, a first chip 32 is attached to thefirst surface 311 of the first substrate 31. In this embodiment, a firstchip 32 is attached to the first surface 311 of the first substrate 31.In Step S203, a plurality of first connecting elements (such as aplurality of first conductive wires 33) electrically connect the firstchip 32 and the first surface 311 of the first substrate 31. In Step204, a plurality of first conductive bodies (such as a plurality offirst solder balls 34) are formed on the first pads 313 on the firstsurface 311 of the first substrate 31. In this embodiment, the firstconductive bodies may be solder balls; however, it may be realized thatthe first conductive bodies can be solder bumps, gold stud bumps, ormetal pins and each in a shape of pillar or column, in addition to ashape of ball.

It should be noted that, in other applications, after Step S201 isperformed, Step S204 is performed and followed by Step S202 and StepS203. That is, the first conductive bodies (such as the first solderballs) may be formed on the first pads 313 on the first surface 311 ofthe first substrate 31 before the first chip 32 is attached to the firstsurface 311 of the first substrate 31. Thereafter, the first conductiveelements (such as the first conductive wires 33) are formed forelectrically connecting the first chip 32 and the first surface 311 ofthe first substrate 31.

Please refer to FIG. 2 and FIG. 4. In Step S205, a first moldingcompound 35 for encapsulating the first surface 311 of the firstsubstrate 31, the first chip 32, the first conductive wires 33, and thefirst solder balls 34. It should be noted that the first moldingcompound 35 encapsulates the entire first surface 311 of the firstsubstrate 31. In this embodiment, the top surface of the first moldingcompound 35 is higher than the top of the first solder balls 34;however, it may be realized that the top surface of the first moldingcompound 35 can be at the same height with the top of the first solderballs 34, or the top surface of the first molding compound 35 can belower than the top of the first solder balls 34.

The included angle between the sidewall of the first molding compound 35and the first substrate 31 is about 85 to 95 degrees, and preferably 90degrees, because the draft angle is almost not needed for the mold inthe present invention. Furthermore, in the present invention, aplurality of the first chips 32 may be encapsulated with the firstmolding compound 35 and thereafter divided into a plurality of packageshaving a shape like tofu. Thereby, the top surface of the first moldingcompound 35 in the packages will not have a mold insert gate mark.

Please refer to FIG. 2 and FIG. 5. In Step S206, a plurality of secondsolder balls 36 are formed on the second pads 314 on the second surface312 of the first substrate 31. It should be noted that this step is anoptional step.

Please refer to FIG. 2 and FIG. 6. In Step S207, a part of a borderportion of the first molding compound 35 is removed, so that the firstmolding compound 35 has at least two heights and one end of each of thefirst solder balls 34 is exposed to make a first package 3. The removalin this step may be accomplished by laser cutting, chemical etching,cutting with a cutting tool, or cutting with a water jet. In this stepof this embodiment, the way of cutting with a cutting tool is used toremove the upper part 351 of the border portion of the first moldingcompound 35, and the lower part 352 of the border portion is remained.The central portion 353 of the first molding compound 35 is not cut awayand is entirely remained.

Therefore, after the cutting, the molding compound 35 has a first heightH₁, a second height H₂, a central portion 353, a lower part 352 of aborder portion, a first top surface 354, and a second top surface 355.The first height Hi is the height of the central portion 353corresponding to the positions of the first chip 32 and the firstconductive wires 33. The second height H₂ is the height of the lowerpart 352 of the border portion corresponding to the positions of thefirst solder balls 34. The first height Hi is greater than the secondheight H₂. The first top surface 354 is corresponding to the firstheight H₁, that is, the first top surface 354 is the top surface of thecentral portion 353. The first top surface 354 has a first surfaceroughness. The second top surface 355 is corresponding to the secondheight H₂, that is, the second top surface 355 is the top surface of thelower part 352 of the border portion. The second top surface 355 has asecond surface roughness. The first surface roughness is different fromthe second surface roughness.

Please refer to FIG. 7 showing a top view of FIG. 6. The second topsurface 355 is a cutting surface and has a plurality of cutting lines 37after the cutting. In the embodiment, the upper parts of the firstsolder balls 34 are removed along with the removal of the upper part 351of the border portion of the first molding compound 35. Therefore, onlythe lower parts of the first solder balls 34 are remained to form ahemispherical shape (as shown in FIG. 6). Furthermore, all the part ofthe molding compound 35 and the parts of the first solder balls 34included in the second top surface 355 have the cutting lines 37. Asshown in FIG. 7, the cutting lines 37 located at each of the four sidesof the second top surface 355 are substantially parallel, and thecutting lines 37 located in each of the four corners of the second topsurface 355 perpendicularly cross each other, since the four corners ofthe second top surface 355 are cut twice.

Please still refer to FIG. 6 showing a schematic diagram the firstpackage of the present invention. The first package 3 comprises a firstsubstrate 31, a first chip 32, a plurality of first connecting elements(such as a plurality of first conductive wires 33), a plurality of firstconductive bodies (such as a plurality of first solder balls 34), afirst molding compound 35, and a plurality of second solder balls 36.The first substrate 31 has a first surface 311, a second surface 312, aplurality of first pads 313 on the first surface 311, and a plurality ofsecond pads 314 on the second surface 312. The first chip 32 is attachedto the first surface 311 of the first substrate 31. In this embodiment,the first chip 32 is attached to the first surface 311 of the firstsubstrate 31. The first conductive wires 33 electrically connect thefirst chip 32 and the first substrate 31. The first solder balls 34 arein a hemispherical shape and disposed on the first pads 313 of the firstsurface 311 of the first substrate 31. The second solder balls 36 aredisposed on the second pads 314 of the second surface 312 of the firstsubstrate 31.

The molding compound 35 encapsulates the first surface 311 of the firstsubstrate 31, the first chip 32, the first conductive wires 33, and thefirst solder balls 34. The molding compound 35 has a first height H₁, asecond height H₂, a central portion 353, a lower part 352 of a borderportion, a first top surface 354, and a second top surface 355. Thefirst height Hi is the height of the central portion 353 correspondingto the positions of the first chip 32 and the first conductive wires 33.The second height H₂ is the height of the lower part 352 of the borderportion corresponding to the positions of the first solder balls 34. Thefirst height H₁ is greater than the second height Hz. The first topsurface 354 is corresponding to the first height H₁, that is, the firsttop surface 354 is the top surface of the central portion 353. The firsttop surface 354 has a first surface roughness. The second top surface355 is corresponding to the second height H₂, that is, the second topsurface 355 is the top surface of the lower part 352 of the borderportion. The second top surface 355 has a second surface roughness. Thefirst surface roughness is different from the second surface roughness.

Please refer to FIG. 7. In this embodiment, the second top surface 355is a cutting surface and has a plurality of cutting lines 37 after thecutting. Furthermore, all the part of the molding compound 35 and theparts of the first solder balls 34 included in the second top surface355 have the cutting lines 37. As shown in FIG. 7, the cutting lines 37located at each of the four sides of the second top surface 355 areparallel, and the cutting lines 37 located in each of the four cornersof the second top surface 355 perpendicularly cross each other, sincethe four corners of the second top surface 355 are cut twice.

Please refer to FIG. 2 and FIG. 8. In Step S208, a second package 4 isstacked on the first solder balls 34 and electrically connected to thefirst solder balls 34, to make a semiconductor device 5. The secondpackage 4 may be any kind of semiconductor packages. In this embodiment,the second package 4 comprises a second substrate 41, a second chip 42,a plurality of second conductive wires 43, a second molding compound 44,and a plurality of third solder balls 45. The second substrate 41 has afirst surface 411 and a second surface 412. The second chip 42 isattached to the first surface 411 of the second substrate 41. The secondconductive wires 43 electrically connect the second chip 42 and thesecond substrate 41. The second molding compound 44 encapsulates thefirst surface 411 of the second substrate 41, the second chip 42, andthe second conductive wires 43. The third solder balls 45 are disposedon the second surface 412 of the second substrate 41 and electricallyconnected to the first solder balls 34.

In this embodiment, the size of the second molding compound 44 of thesecond package 4 is the same as that of the first molding compound 35 ofthe first package 3. Thus, only one molding machine is required toperform both the molding processes for the second package 4 and thefirst package 3. As a result, the production cost can be reduced. Inaddition, in the molding process for the first package 3, the firstmolding compound encapsulates the entire first surface 311 of the firstsubstrate 31, and accordingly the pads on the first surface 311 are notpolluted.

Please still refer to FIG. 8, showing a schematic diagram of thesemiconductor device according to the present invention. Thesemiconductor device 5 comprises a first package 3 and a second package4. The second package 4 is stacked on the first package 3. The firstpackage 3 comprises a first substrate 31, a first chip 32, a pluralityof first connecting elements (such as a plurality of first conductivewires 33), a plurality of first conductive bodies (such as a pluralityof first solder balls 34), a first molding compound 35, and a pluralityof second solder balls 36. The first substrate 31 has a first surface311, a second surface 312, a plurality of first pads 313 on the firstsurface 311, and a plurality of second pads 314 on the second surface312. The first chip 32 is attached to the first surface 311 of the firstsubstrate 31. The first conductive wires 33 electrically connect thefirst chip 32 and the first substrate 31. The first solder balls 34 arein a hemispherical shape and disposed on the first pads 313 of the firstsurface 311 of the first substrate 31.

The molding compound 35 encapsulates the first surface 311 of the firstsubstrate 31, the first chip 32, the first conductive wires 33, and thefirst solder balls 34. The molding compound 35 has a first height H₁, asecond height H₂, a central portion 353, a lower part 352 of a borderportion, a first top surface 354, and a second top surface 355. Thefirst height H₁ is the height of the central portion 353 correspondingto the positions of the first chip 32 and the first conductive wires 33.The second height H₂ is the height of the lower part 352 of the borderportion corresponding to the positions of the first solder balls 34. Thefirst height Hi is greater than the second height H₂. The first topsurface 354 is corresponding to the first height H₁, that is, the firsttop surface 354 is the top surface of the central portion 353. The firsttop surface 354 has a first surface roughness. The second top surface355 is corresponding to the second height H₂, that is, the second topsurface 355 is the top surface of the lower part 352 of the borderportion. The second top surface 355 has a second surface roughness. Thefirst surface roughness is different from the second surface roughness.

Please also refer to FIG. 7. In this embodiment, the second top surface355 is a cutting surface and has a plurality of cutting lines 37 afterthe cutting. Furthermore, all the part of the molding compound 35 andthe parts of the first solder balls 34 included in the second topsurface 355 have the cutting lines 37. As shown in FIG. 7, the cuttinglines 37 located at each of the four sides of the second top surface 355are parallel, and the cutting lines 37 located in each of the fourcorners of the second top surface 355 perpendicularly cross each other,since the four corners of the second top surface 355 are cut twice.

The second package 4 comprises a second substrate 41, a second chip 42,a plurality of second conductive wires 43, a second molding compound 44,and a plurality of third solder balls 45. The second substrate 41 has afirst surface 411 and a second surface 412. The second chip 42 isattached to the first surface 411 of the second substrate 41. The secondconductive wires 43 electrically connect the second chip 42 and thesecond substrate 41. The second molding compound 44 encapsulates thefirst surface 411 of the second substrate 41, the second chip 42, andthe second conductive wires 43. The third solder balls 45 are disposedon the second surface 412 of the second substrate 41 and electricallyconnected to the first solder balls 34.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention.

1-19. (canceled)
 20. A semiconductor package, comprising: a substrateincluding a top patterned conductive layer at a top surface of thesubstrate, the top patterned conductive layer defining a plurality oftop pads; a plurality of conductive components positioned oncorresponding ones of the top pads; a chip positioned on the top surfaceof the substrate and electrically connected to the top patternedconductive layer; and a molding compound encapsulating the chip, the toppatterned conductive layer, and the plurality of conductive components,wherein: the molding compound extends laterally to edges of thesubstrate; the molding compound at a central portion of the substratehas a first height, and the central portion extends beyond a peripheryof the chip; the molding compound in a border area between the centralportion and the edges of the substrate has a second height less thanhalf of the first height; and the molding compound in the border areaexposes and is coplanar with a top surface of at least one of theplurality of conductive components.
 21. The semiconductor package ofclaim 20, wherein the top pads are arranged in multiple rows surroundingthe chip.
 22. The semiconductor package of claim 20, wherein theconductive components are arranged in multiple rows surrounding thechip.
 23. The semiconductor package of claim 20, wherein the conductivecomponents include solder.
 24. The semiconductor package of claim 20,wherein the bottom patterned conductive layer is substantially coplanarwith the bottom surface of the substrate.
 25. The semiconductor packageof claim 20, wherein each of the conductive components has ahemispherical shape.
 26. The semiconductor package of claim 20, whereina top surface extending across the border area includes cut marks.
 27. Asemiconductor device, comprising: a semiconductor package including achip, conductive components, and a molding compound including a centralportion and a border portion, wherein: the central portion fullyencapsulates the chip, and the central portion has a first heightgreater than the height of the chip; the border portion extends betweenthe central portion and an external periphery of the package, andwherein: the border portion has a second height less than the firstheight, a top surface across the extent of the border portion includesmarks incurred by removal of a portion of the molding compound, and thetop surface exposes the conductive components embedded in the moldingcompound.
 28. The semiconductor device of claim 27, wherein the secondheight is less than half of the first height.
 29. The semiconductordevice of claim 27, further comprising solder balls at a lower surfaceof the semiconductor package.
 30. The semiconductor device of claim 27,further comprising a substrate and a patterned conductive layer, whereinthe chip is positioned on the substrate and is electrically connected tothe patterned conductive layer, and the conductive components arepositioned on pads defined by the patterned conductive layer.
 31. Thesemiconductor device of claim 27, wherein the semiconductor package is afirst package, further comprising a second package stacked on the firstpackage, and the second package is electrically coupled to the firstpackage through the conductive components.
 32. The semiconductor deviceof claim 31, wherein the second package is electrically coupled to thefirst package through the conductive components by way of a plurality ofsolder balls positioned at a lower surface of the second package andcontacting respective ones of the conductive components.
 33. A method offorming a stackable package, comprising: positioning conductive elementson respective top pads in a top surface of a substrate; mounting a chipon the top surface of the substrate; applying a molding compound overthe top surface of the substrate to a first height, including applyingthe molding compound over the chip, the top pads, and the conductiveelements; and cutting the molding compound in a border area around acircumference of the package to a second height less than the firstheight, wherein the second height is less than an original height of theconductive elements, and wherein the conductive elements are exposed inthe border area by the cutting.
 34. The method of claim 33, wherein thecutting includes removing a part of each of the conductive elements,such that at least one of the conductive elements has a hemisphericalshape.
 35. The method of claim 33, wherein subsequent to the cutting,the molding compound in a central area has the first height.